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LTC4221 Dual Hot Swap Controller/ Power Sequencer with Dual Speed, Dual Level Fault Protection
FEATURES

DESCRIPTIO
Allows Safe Board Insertion and Removal from a Live Backplane Configurable Power Supply Sequencing Soft-Start with Current Foldback Limits Inrush Current No External Gate Capacitor Required Adjustable Dual Level Circuit Breaker Protection Controls Supply Voltages from 1V to 13.5V Independent N-Channel MOSFET High Side Drivers FB Pin Monitors VOUT for Overvoltage Protection Latch Off or Automatic Retry on Current Fault FAULT and PWRGD Outputs Narrow 16-Pin SSOP Package
The LTC(R)4221 is a 2-channel Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. Using two independent high side gate drivers to control two external N-channel pass transistors, the output voltages can be ramped up with current foldback to limit the inrush current during the start-up period. No external compensation capacitors are required at the GATE pins. The two channels can be configured to ramp up and down separately or simultaneously for supply voltages ranging from 2.7V to 13.5V and 1V to 13.5V for channels 1 and 2 respectively. Each channel has two current limit comparators that provide dual level and dual speed overcurrent circuit breaker protection after the start-up period. If any current sense voltage exceeds 100mV for 1s or 25mV for the timeout delay (set by the CFILTER at the FILTER pin), then the FAULT latch is set and both GATE pins are pulled low. The FB pins monitor the respective channel output voltages and provide the inputs for the PWRGD comparators as well as overvoltage protection.
APPLICATIO S

Electronic Circuit Breaker Power Supply Sequencing Live Board Insertion and Removal Industrial High Side Switch/Circuit Breaker
, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) LONG
2-Channel Hot Swap Controller
VCC1 3.3V VCC2 2.5V
0.004 10 100nF * 100nF 10
IRF7413 0.004 IRF7413
LONG
*
SHORT
21k 10k
VCC1 ON1
SENSE1 GATE1 VCC2
SENSE2 GATE2 14.3k FB2
5.11k 10k 10k
SHORT
13.3k
ON2
10k
LTC4221
FAULT GND TIMER
470nF
FAULT GND
SHORT LONG *SMAJ10 (OPTIONAL)
FILTER
1nF
U
VOUT1 3.3V/5A VOUT2 2.5V/5A PWRGD2 PWRGD1
20k
U
U
PWRGD2 PWRGD1
FB1
5.11k
4221 TA01
4221f
1
LTC4221
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW ON1 VCC1 SENSE1 GATE1 FB1 PWRGD1 FAULT FILTER 1 2 3 4 5 6 7 8 16 ON2 15 VCC2 14 SENSE2 13 GATE2 12 FB2 11 PWRGD2 10 GND 9 TIMER
Supply Voltage (VCCn) ............................................ 17V SENSEn Pins ............................ - 0.3V to (VCCn + 0.3V) FB, ON Pins .............................. - 0.3V to (VCC1 + 0.3V) TIMER Pin .................................................. - 0.3V to 2V GATE Pins (Note 3) ................................... - 0.3V to 21V PWRGD, FAULT, FILTER Pins ................... - 0.3V to 17V Operating Temperature Range LTC4221C ............................................... 0C to 70C LTC4221I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC4221CGN LTC4221IGN GN PART MARKING 4221 4221I
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 130C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VCC1 VCC2 ICC1 ICC2 VCC1(UVL) VCC1(HYST) VCC2(UVL) VCC2(HYST) ISENSE1(IN) ISENSE2(IN) VSENSE(FC) VSENSE(SC) VSENSE(ACL) IGATE(UP) IGATE(DN) IGATE(FSTDN) VGATE PARAMETER Supply Voltage Channel 1 Supply Voltage Channel 2 VCC1 Supply Current VCC2 Supply Current Undervoltage Lockout for Channel 1 Undervoltage Lockout Hysteresis Undervoltage Lockout for Channel 2 Undervoltage Lockout Hysteresis SENSE1 Pin Input Current SENSE2 Pin Input Current SENSEn Threshold Voltage SENSEn Threshold Voltage SENSEn Voltage at Active Current Limit GATEn Output Current GATEn Output Current GATEn Output Current External N-Channel Gate Drive
The indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC1 = 5V, VCC2 = 3.3V, unless otherwise noted.
CONDITIONS
MIN 2.7 1

TYP
MAX 13.5 13.5
UNITS V V mA mA V mV V mV A A A mV mV mV mV mV
VCC2 VCC1 ON1, ON2 = 2V ON1, ON2 = 2V VCC1 Rising VCC2 Rising 0V VSENSE1 VCC1 VSENSE2 = VCC2 VSENSE2 = 0V Channeln Fast Comparator Threshold Channeln Slow Comparator Threshold VFBn = 0 VFBn = 0.65V VON1 = VON2 = 2V, VGATEn = 0V VON1 = VON2 = 0.6V, VGATEn = 3.3V UVLO with VGATEn = 3.3V or FAULT Latched with VGATEn = 3.3V VGATEn - VCC1 for VCC1 = 2.7V, VCC2 = 1V VGATEn - VCC1 for VCC1 = 3.3V, VCC2 = 2.5V VGATEn - VCC1 for VCC1 = 5V, VCC2 = 3.3V VGATEn - VCC1 for VCC1 = 12V, VCC2 = 12V 0V VONn VCC1 VON1 Falling
2.2 0.05 2.1 0.65 2.5 110 0.8 25 0.03 0.2 1000 85 22.5 20.5 100 25 25 9 25
3 0.15 2.675 0.975 5 5 115 27.5 29.5

-7 75
-9.5 100 16
-12 125

4.5 5 8 7 0.4 0.01 0.375 0.4 25
13 16 16 18 0.5 1 0.425
VGATE(OV) ION(IN) VON(RESET) VON(RESETHYST)
GATEn Overvoltage Lockout Threshold ONn Pin Input Current ON1 Reset Threshold ON1 Reset Threshold Hysteresis
2
U
W
U
U
WW
W
A A mA V V V V V A V mV
4221f
LTC4221
ELECTRICAL CHARACTERISTICS
SYMBOL VON(OFF) VON(OFFHYST) IFB(IN) VFB(UV) VFB(UVHYST) VFB(LREG) VFB(OV) IFILTER(UP) IFILTER(DN) VFILTER(TH) VFILTER(HYST) ITMR(UP1) ITMR(UP2) ITMR(FSTDN) VTMR(H) VTMR(L) IFAULT(UP) VFAULT(TH) VFAULT(HYST) VFAULT(OL) IPWRGD(LK) VPWRGD(OL) tP(FC-GATE) tP(SC-FAULT) tP(FAULT-GATE) tP(OV-GATE) tP(FILTER-GATE) tRESET tP(ON-GATE) PARAMETER ONn Off Threshold ONn Off Threshold Hysteresis FBn Input Current FBn Undervoltage Threshold FBn Undervoltage Threshold Hysteresis FBn Threshold Line Regulation FBn Overvoltage Threshold FILTER Pull-Up Current FILTER Pull-Down Current FILTER Threshold FILTER Threshold Hysteresis TIMER Pull-Up Current 1 TIMER Pull-Up Current 2 TIMER Pull-Down Current TIMER High Threshold TIMER Low Threshold FAULT Pull-Up Current FAULT Threshold FAULT Hysteresis FAULT Output Low Voltage PWRGDn Leakage Current PWRGDn Output Low Voltage Fast Comparator Trip to GATEn Discharging Slow Comparator Trip to FILTER High and FAULT Latched FAULT Low to GATEn Discharging FBn OV Comparator Trip to GATEn Discharging Filter Comparator Trip to GATEn Discharging Circuit Breaker Reset Delay Time Turn Off Propagation Delay
The indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC1 = 5V, VCC2 = 3.3V, unless otherwise noted.
CONDITIONS High to Low, GATEn Turns Off by 100A Pull-Down 0V VFBn VCCn FBn Falling 2.7V VCC1 13.5V FBn Rising During Current Fault Condition During Normal Cycle Latched Off Threshold, FILTER Rising Initial Timing Cycle Start-Up Cycle VTIMER = 1.5V, End of Initial Timing Cycle TIMER Rising TIMER Falling FAULT Falling IFAULT = 1.6mA, VCC1 = 5V VPWRGDn = VCC1, VFBn = 0.7V, Normal Cycle IPWRGDn = 1.6mA, VCC1 = 5V, VFBn = 0V, Normal Cycle VSENSEn = VCCn to (VCCn - 200mV) Step VSENSEn = VCCn to (VCCn - 50mV) Step. FILTER Open VFAULT = 3.3V to 0V VFBn = 0V to 1V VFILTER = 0V to 1.5V VON1 < 0.4V to FAULT High VONn 0.821V to GATEn Discharging

MIN 0.796
TYP 0.821 30
MAX 0.846
UNITS V mV

0.01 0.605 0.617 3 2 0.805 -80 1.15 1.18 -1.2 -15 1.172 0.1 -2.5 0.791 0.822 -105 1.8 1.24 105 -1.9 -20 9 1.234 0.4 -3.8 0.816 35 0.14 0.01 0.14 1 15 15 18 15 15 15
1 0.629
A V mV mV
0.838 -132 2.45 1.30 -2.6 -25 1.27 0.5 -5 0.841 0.4 10 0.4 1.5 35 35 35 35 30 35
V A A V mV A A mA V V A V mV V A V s s s s s s s
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All current into device pins are positive. All voltages are referenced to ground unless otherwise specified.
Note 3: An internal zener on each GATE pin clamps the charge pump voltage to a typical maximum operating voltage of 26V. External overdrive of either GATE pin beyond its internal zener voltage may damage the device.
4221f
3
LTC4221 TYPICAL PERFOR A CE CHARACTERISTICS
ICC1 vs Temperature
6 5 4
ICC1 (mA)
VCC2 = 1V VCC1 = 13.5V
ICC2 (mA)
0.125 0.100 0.075 0.050 0.025 0 - 50 - 25 0
VCC1(UVL) (V)
VCC1 = 12V
3 VCC1 = 5V 2 VCC1 = 2.7V 1 0 -50 -25
50 25 75 0 TEMPERATURE (C)
VCC2(UVL) vs Temperature
0.815 0.810 0.805 RISING TIMER = 0.3V
|ISENSE2(IN)| (A)
VCC2(UVL) (V)
10 1 0.1 0.01
VSENSE(FC) (mV)
0.800 0.795 0.790 0.785 0.780 0.775 0.770 -50 -25
FALLING
0 25 50 75 TEMPERATURE (C)
VSENSE(FC) vs Temperature
102.0 101.5
VSENSE(SC) (mV) VSENSE(FC) (mV)
VCC1 = 5V VCC2 = 3.3V
VSENSE(SC) (mV)
101.0 100.5 100.0 99.5 99.0 -50 -25
50 25 75 0 TEMPERATURE (C)
4
UW
100
100
ICC2 vs Temperature
0.200 0.175 0.150 VCC2 = 12V VCC1 = 13.5V VCC2 = 13.5V 2.52 2.50 2.48 2.46 2.44 2.42 2.40 2.38 50 75 25 TEMPERATURE (C) 100 125
VCC1(UVL) vs Temperature
TIMER = 0.3V RISING
VCC2 = 5V VCC2 = 3.3V VCC2 = 1V
FALLING
125
2.36 - 50 - 25
0
50 75 25 TEMPERATURE (C)
100
125
4221 G01
4221 G02
4221 G03
|ISENSE2(IN)| vs VSENSE2
10000 1000 100
101.5 101.0 102.0
VSENSE(FC) vs VCC1
VCC2 = VCC1 TA = 25C
100.5
0.001 0.0001
125
VCC1 = 2.7V, VCC2 = 1V VCC1 = 5V, VCC2 = 3.3V VCC1 = 13.5V, VCC2 = 13.5V 0 2 4 6 8 10 12
4221 G05
100.0
99.5 0 2 4 6 8 VCC1 (V)
4221 G06
10
12
14
16
VSENSE2 (V)
4221 G04
VSENSE(SC) vs VCC1
25.6 25.4 25.2 25.0 24.8 24.6 24.4 24.2 100 125 0 2 4 6 8 VCC1 (V)
4221 G07 4221 G08
VSENSE(SC) vs Temperature
VCC2 = VCC1 TA = 25C 26.0 VCC1 = 5V 25.8 VCC2 = 3.3V 25.6 25.4 25.2 25.0 24.8 24.6 10 12 14 16 24.4 - 50 - 25 0 50 75 25 TEMPERATURE (C) 100 125
4221 G09
4221f
LTC4221 TYPICAL PERFOR A CE CHARACTERISTICS
VSENSE(ACL) vs VFB
30 VCC1 = 5V VCC2 = 3.3V 25 TA = 25C
VSENSE(ACL) (mV)
IGATE(DN) (A)
IGATE(UP) (A)
20 15 10 5 0 0 0.1 0.2 0.3 0.4 VFB (V) 0.5 0.6 0.7
IGATE(FSTDN) vs Temperature
60 50
IGATE(FSTDN) (mA)
VCC2 = 1V VGATE = 3.3V
VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V
40
VGATE1 (V)
VGATEn (V)
30 20 10
0 -50 -25
50 25 75 0 TEMPERATURE (C)
VGATE2 (VGATE2 - VCC1) vs Temperature
16 14 12
VGATE2 (V)
VCC1 = 2.7V, VCC2 = 1V VCC1 = 5V, VCC2 = 3.3V VCC1 = 13.5V, VCC2 = 13.5V
VON(RESET) (V)
VGATE(OV) (V)
10 8 6
4 -50 -25
50 25 75 0 TEMPERATURE (C)
UW
100 100
IGATE(UP) vs Temperature
-6 -7 -8 -9 -10 -11 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 50 25 75 0 TEMPERATURE (C) 100 125 VCC2 = 1V VGATE = 0V 104 103 102 101 100 99 98
IGATE(DN) vs Temperature
VCC2 = 1V VGATE = 3.3V
-12 -50 -25
97 -50 -25
VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 50 25 75 0 TEMPERATURE (C) 100 125
4221 G10
4221 G11
4221 G12
VGATEn (VGATEn - VCC1) vs VCC1
15 14 13 12 11 10 9 8 7 VCC2 = VCC1 - 1.5V TA = 25C VGATE1
VGATE1 (VGATE1 - VCC1) vs Temperature
18 16 14 VCC1 = 2.7V, VCC2 = 1V VCC1 = 5V, VCC2 = 3.3V VCC1 = 13.5V, VCC2 = 13.5V
VGATE2
12 10 8 6 4 -50 -25
125
6 0 2 4 6 8 VCC1 (V) 10 12 14
50 25 75 0 TEMPERATURE (C)
100
125
4221 G13
4221 G14
4221 G15
VGATE(OV) vs Temperature
0.420 0.415 0.410 0.405 0.400 0.395 0.390 0.385 0.380 VCC2 = 1V TIMER = 0.5V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V
VON(RESET) vs VCC1
0.430 0.425 RISING 0.420 0.415 0.410 0.405 FALLING 0.400 0.395 VCC2 = 1V, TA = 25C
125
0.375 -50
-25
0 25 75 50 TEMPERATURE (C)
100
125
0
2
4
6
8 VCC1 (V)
10
12
14
16
4221 G16
4221 G17
4221 G18
4221f
5
LTC4221 TYPICAL PERFOR A CE CHARACTERISTICS
VON(RESET) vs Temperature
0.440 0.435 0.430 VCC1 = 5V VCC2 = 3.3V RISING
VON(RESET) (V)
0.425
VON(OFF) (V)
0.420 0.415 0.410 0.405 FALLING 0.400 0.395 -50 -25 0 25 75 50 TEMPERATURE (C) 100 125
0.840 0.835 0.830 0.825 FALLING 0.820 0.815 0 2 4 6 8
VCC1 (V)
VON(OFF) (V)
VFB(UV) vs VCC1
0.622
0.623
VCC2 = 1V 0.621 TA = 25C 0.620
VFB(UV) (V)
RISING
VFB(UV) (V)
VFB(OV) (V)
0.619 0.618 0.617 0.616 0.615 0.614 0 2 4 6 8 VCC1 (V)
4221 G22
FALLING
10
VFB(OV) vs Temperature
0.825 VCC1 = 5V 0.824 VCC2 = 3.3V 0.823 0.822 VFB(OV) (V) 0.821 0.820 0.819 0.818 0.817 0.816 0.815 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
IFILTER(DN) (A)
IFILTER(UP) (A)
6
UW
12 14
VON(OFF) vs VCC1
0.860 0.855 RISING 0.850 0.845 0.85 0.84 0.83 VCC2 = 1V TA = 25C 0.87 0.86
VON(OFF) vs Temperature
VCC1 = 5V VCC2 = 3.3V RISING
FALLING 0.82 0.81 -50 -25
10
12
14
16
50 25 75 0 TEMPERATURE (C)
100
125
4221 G19
4221 G20
4221 G21
VFB(UV) vs Temperature
VCC1 = 5V 0.622 VCC2 = 3.3V 0.621 0.620 0.619 0.618 0.617 0.616 0.615 0.614 FALLING
VFB(OV) vs VCC1
0.8225 0.8220 0.8215 0.8210 0.8205 0.8200 0.8195 0.8190 0 2 4 6 8
VCC1 (V)
4221 G23 4221 G24
RISING
VCC2 = 1V TA = 25C
16
0.613 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
10
12
14
16
IFILTER(UP) vs Temperature
-88 -93 -98 -103 -108 -113 -118 -50 -25 VCC2 = 1V VFILTER = 1V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 2.00 1.95 1.90 1.85 1.80 1.75 1.70
IFILTER(DN) vs Temperature
VCC2 = 1V VFILTER = 1V
50 25 75 0 TEMPERATURE (C)
100
125
1.65 -50 -25
VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 50 25 75 0 TEMPERATURE (C) 100 125
4221 G25
4221 G26
4221 G27
4221f
LTC4221 TYPICAL PERFOR A CE CHARACTERISTICS
VFILTER(TH) vs Temperature
1.246 VCC2 = 1V 1.244 V GATE1 = 0.2V 1.242 1.240 VFILTER(TH) (V)
ITMR(UP1) (A)
ITMR(UP2) (A)
1.238 1.236 1.234 1.232 1.230 1.228 1.226 1.224 -50 -25 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 50 25 0 75 TEMPERATURE (C) 100 125
ITMR(FSTDN) vs Temperature
25 VCC2 = 1V VTMR = 1.5V 20 1.240 1.238 1.236 1.234 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V
ITMR(FSTDN) (mA)
1.230 1.228 1.226
VTMR(L) (V)
15
VTMR(H) (V)
10
5
0 -50
-25
50 25 0 75 TEMPERATURE (C)
IFAULT(UP) vs Temperature
-3.1 -3.3 -3.5 VCC2 = 1V VFAULT = 1.5V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V
0.860 0.855 0.850 0.845 VFAULT(TH) (V) 0.840 0.835 0.830 0.825 0.820
IFAULT(UP) (A)
-3.7 -3.9 -4.1 -4.3 -4.5 -50 -25
VFAULT(TH) (V)
50 25 75 0 TEMPERATURE (C)
UW
100
ITMR(UP1) vs Temperature
-1.6 -1.7 -1.8 -1.9 -2.0 -2.1 -2.2 -50 -25
ITMR(UP2) vs Temperature
-17.0 VCC2 = 1V -17.5 VTMR = 0.25V -18.0 -18.5 -19.0 -19.5 -20.0 -20.5 -21.0 -21.5 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V
VCC2 = 1V VTMR = 0.25V
VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V
50 25 75 0 TEMPERATURE (C)
100
125
-22.0 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
4221 G28
4221 G29
4221 G30
VTMR(H) vs Temperature
VCC2 = 1V
VTMR(L) vs Temperature
0.404 0.403 0.402 0.401 0.400 0.399 0.398
VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V
VCC2 = 1V
VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V
1.232
1.224 1.222 125 1.220 -50 -25
0.397 0.396 - 50 - 25 0 50 75 25 TEMPERATURE (C) 100 125
50 25 0 75 TEMPERATURE (C)
100
125
4221 G31
4221 G32
4221 G33
VFAULT(TH) vs VCC1
RISING VCC2 = 1V TA = 25C
VFAULT(TH) vs Temperature
0.87 0.86 0.85 0.84 0.83 0.82 FALLING VCC1 = 5V VCC2 = 3.3V RISING
FALLING
0.815 0.810
0.81 0.80 -50 -25
100
125
0
2
4
6
8 VCC1 (V)
10
12
14
16
50 25 75 0 TEMPERATURE (C)
100
125
4221 G34
4221 G35
4221 G36
4221f
7
LTC4221 TYPICAL PERFOR A CE CHARACTERISTICS
VPWRGD(OL)/VFAULT(OL) vs Temperature
0.500 0.450 VCC2 = 1V, IPWRGD/IFAULT = 1.6mA VCC1 = 2.7V VCC1 = 5V 0.400 VCC1 = 13.5V 0.350
tp(SC-FAULT) (V)
VOL (V)
0.300 0.250 0.200 0.150 0.100 0.050 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
15 14 13 12 -50 -25
tp(FC-GATE) (V)
PI FU CTIO S
ON1 (Pin 1): System/Channel 1 On Input. Both GATE pins are pulled low by internal 100A pull-downs and the FAULT latch is reset when VON1 < 0.4V. When 0.425V < VON1 < 0.821V, the FAULT latch is released from reset. When VON1 > 0.851V, GATE1 ramps up after an initial timing cycle. VCC1 (Pin 2): Channel 1 Positive Supply Input. It powers all the internal circuitry. VCC1 can range from 2.7V to 13.5V for normal operation but it must be VCC2. An undervoltage lockout circuit disables both channels whenever the voltage at VCC1 is less than 2.5V. SENSE1 (Pin 3): Channel 1 Current Sense Input. A sense resistor RSENSE1 is placed in the supply path between VCC1 and SENSE1 to sense channel 1 load current. If VRSENSE1 exceeds 100mV for more than 1s or 25mV for an adjustable time (set by the CFILTER), the FAULT latch is set and fast pull-down circuits are triggered to discharge both GATEs low. During the start-up cycle, GATE1 ramp-up is controlled to servo VRSENSE1 VSENSE(ACL). VSENSE(ACL) increases from 9mV to 25mV as VFB1 ramps from 0V to 0.5V. To disable the current limit and circuit breaker function for channel 1, tie SENSE1 to VCC1. GATE1 (Pin 4): Channel 1 Gate Drive. This pin is the high side gate drive of an external N-channel MOSFET. When VON1 < 0.821V, GATE1 is held low by a 100A current source. When VON1 > 0.851V, an initial timing cycle is followed by a start-up cycle when an internal charge pump provides a 9.5A pull-up to ramp up GATE1 with inrush current limiting. UVLO, overvoltage, overcurrent and externally generated faults override the ON1 pin and pull GATE1 low. FB1 (Pin 5): VOUT1 Feedback Input. FB1 monitors the channel 1 output voltage with an external resistive divider. When VFB1 < 0.617V, the PWRGD1 pin is pulled low. When VFB1 > 0.822V, overvoltage is detected, the FAULT latch is set and both GATEs are pulled low. The FB1 pin is also used to control the channel 1 current limit during its start-up cycle. PWRGD1 (Pin 6): Channel 1 Power Good Output. PWRGD1 is pulled low when VFB1 < 0.617V, during the initial timing cycle or when the chip is in UVLO. An external pull-up is required to generate a logic high at the open-drain PWRGD1 pin.
8
UW
tp(SC-FAULT) vs Temperature
18 17 16 VCC2 = 1V TIMER = 0.5V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 1.8 1.6 1.4 1.2 1.0 0.8
tp(FC-GATE) vs Temperature
VCC2 = 1V TIMER = 0.5V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V
50 25 75 0 TEMPERATURE (C)
100
125
0.6 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
4221 G37
4221 G38
4221 G39
U
U
U
4221f
LTC4221
PI FU CTIO S
FAULT (Pin 7): Fault Status Input/Output. FAULT is a bidirectional pin. As an input, pulsing VFAULT < 0.816V will set the FAULT latch and bring the LTC4221 into the fault state. As an output, FAULT is pulled high by an internal 3.8A pull-up under normal operating conditions. When an overcurrent fault is detected by a SENSE pin or a overvoltage fault detected by an FB pin, the FAULT latch is set and the LTC4221 goes into the fault state. The FAULT latch is reset by a UVLO or the ON1 pin being driven below 0.4V. FILTER (Pin 8): Overcurrent Fault Timing Filter. The FILTER pin requires an external capacitor to ground to adjust the response time of the two slow comparators. The FILTER pin can be left unconnected for a default slow comparator response time of 15s. TIMER (Pin 9): Analog System Timer. The TIMER pin requires an external capacitor to ground to generate timing delay cycles during start-up. The LTC4221's initial and start-up timing cycles are controlled by CTIMER and the internal current sources connected to the TIMER pin. GND (Pin 10): Ground. Connect to a ground plane for optimum performance. PWRGD2 (Pin 11): Channel 2 Power Good Output. Similar functionality as PWRGD1. Controlled by FB2. FB2 (Pin 12): VOUT2 Feedback Input. Similar functionality as FB1. Monitors channel 2 output voltage, controls PWRGD2 output and channel 2 start-up current limit. GATE2 (Pin 13): Channel 2 Gate Drive. Similar functionality as GATE1. Controls the gate drive of the channel 2 external N-channel MOSFET. ON2 controls GATE2 in the same manner as ON1 controls GATE1. VON1 < 0.4V overrides conditions at ON2 and GATE2 is held low by a 100A current source. UVLO, overvoltage, overcurrent and externally generated faults override conditions at ON1 and ON2, and pull GATE2 low. SENSE2 (Pin 14): Channel 2 Current Sense Input. Similar functionality as SENSE1. Monitors channel 2 load current through RSENSE2 placed in the supply path between VCC2 and SENSE2. To disable the current limit and circuit breaker function for channel 2, tie SENSE2 to VCC2. VCC2 (Pin 15): Channel 2 Positive Supply Input. VCC2 can range from 1V to 13.5V for normal operation but it must be VCC1. An undervoltage lockout circuit disables both channels whenever the voltage at VCC2 is less than 0.8V. ON2 (Pin 16): Channel 2 On Input. GATE2 is pulled to ground by a 100A current source when VON2 < 0.821V. When VON2 > 0.851V, GATE2 ramps up after an initial timing cycle.
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4221f
9
LTC4221
BLOCK DIAGRA
OSCILLATOR VCC1 ON1 1 0.821V 0.4V ON2 16 CHARGE PUMP 2 CPO2
VCC1
VCC1 0.821V 105A
FILTER
8 1.24V 1.8A
VCC1 3.8A 0.816V FAULT 7
VCC1
VCC1
2
+ -
VCC1
9mV TO 25mV
+ -
SENSE1 3
100mV
0.617V FB1 5
VCC2
VCC2 15
+ -
VCC2
9mV TO 25mV
+ -
SENSE2 14
100mV
0.617V FB2 12
10
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CHARGE PUMP 1 CPO1 VCC1 VCC2 UVLO VCC1 20A ON1 COMPARATOR VCC1 1.9A
- + - +
9 TIMER
ON2 COMPARATOR
+ -
FTRHI FILTER COMPARATOR
SYSTEM CONTROL LOGIC TMRHI
+
1.234V 0.4V
- TMRHI COMPARATOR
TMRLO
+
- TMRLO COMPARATOR + -
FAULT_LO FAULT COMPARATOR 12V 10 GND CPO1
9.5A 4 GATE1 VCC1 26V
+ - +
SLOWHI1
CUR_LIMIT1
SLOW COMPARATOR 1
FPD1 109.5A
FASTHI1 CHANNEL 1 CONTROL - FAST LOGIC COMPARATOR 1
+
0.822V
GATELO1 OV1 COMPARATOR GATELO1 COMPARATOR
+ -
0.4V
-
+
FB1 COMPARATOR
6 PWRGD1
-
CPO2 12V
CHANNEL ONE 9.5A 13 GATE2
VCC2
26V
+ - +
SLOWHI2
CUR_LIMIT2
SLOW COMPARATOR 2
FPD2 109.5A
FASTHI2 CHANNEL 2 CONTROL - FAST LOGIC COMPARATOR 2
+
0.822V
GATELO2 OV2 COMPARATOR GATELO2 COMPARATOR
+ -
0.4V
-
+
FB2 COMPARATOR
11 PWRGD2
-
CHANNEL TWO
4221 BD
4221f
LTC4221
OPERATIO
Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current may damage the connector pins and glitch the power bus, causing other boards in the system to reset. The LTC4221 is designed to turn on and off a circuit board's supply voltages in a controlled manner, allowing insertion or removal without glitches or connector damage. The LTC4221 can reside on the backplane or on the removable circuit board for hot insertion applications. It controls the path between the backplane power bus and the daughter board load with an external MOSFET switch. Both inrush control and short-circuit protection are provided by the external MOSFET. Each LTC4221 controls two channels, each with its individual MOSFET for supplies from 1V to 13.5V. Overview The timing diagram in Figure 1 shows some typical waveforms of the LTC4221. The VCC and GND pins receive power through the longest connector pins and are the first to connect when the board is inserted. During the undervoltage lockout (UVLO) state before time point 1, both GATE pins are held low by internal N-channel MOSFET pull-downs, turning the external MOSFETs off. Once both VCC pins are valid at time point 1, the LTC4221 enters into a reset state as ON1 is below its reset threshold. At time point 2, ON1 clears its reset threshold and the device goes from the reset state to an off state. When either ON1 or ON2 clears its off threshold, both GATE pins are < 0.4V and TIMER < 0.4V (time points 3 and 4), the TIMER pin sources 1.9A and an initial timing cycle starts. Any transition of ON1 and ON2 through their off thresholds will reset the initial timing cycle. At time point 5, TIMER reaches its high threshold and is pulled down by an internal N-channel MOSFET to its low threshold at time point 6. The LTC4221 then checks that FILTER pin voltage is low and FAULT pin voltage is high. If both conditions are met, the electronic circuit breaker is armed. The channel 1 start-up timing cycle starts at time point 6 since ON1 has cleared its off threshold and ON2 has not.
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During the start-up cycle, TIMER sources 20A and GATE1 sources 9.5A. As GATE1 ramps up, MOSFET1 starts to turn on and current flows through to charge up the load capacitance. As VOUT1 and FB1 ramp up, the load current is monitored through the external SENSE1 resistor. Between time points 7 and 8, the GATE1 9.5A pull-up is controlled to servo the voltage across RSENSE1 to be less than the SENSE1 active current limit voltage, which has a component controlled by the FB1 voltage (see Applications Information: Start-Up Cycle with Current Limit). In this way, inrush current is limited and MOSFET1 does not overheat during the start-up cycle. When FB1 clears its undervoltage threshold, PWRGD1 asserts high. At time point 9, TIMER reaches its high threshold and is pulled down by an internal N-channel MOSFET to its low threshold at time point 10. Channel 1's slow comparator is armed at time point 9 and enters a fault monitor mode, bringing the channel 1 start-up cycle to an end. At time point 10, ON2 voltage is monitored and since ON2 has cleared its off threshold, the start-up timing cycle repeats for channel 2. The inrush current is low and GATE2 ramps up without need for current limiting. Channel 2's slow comparator is armed at time point 11 and enters a fault monitor mode, ending the channel 2 start-up cycle. Overcurrent faults translate to an increase in either VRSENSE. At time point 13, VRSENSE1 > 25mV (slow comparator threshold). The 1.8A pull-down on the FILTER changes to a 105A pull-up. When the FILTER pin hits its threshold at time point 14, it triggers a fault state when FAULT is latched low and both GATE pins are pulled low by internal N-channel MOSFETs, turning off the external MOSFETs. As each channel output discharges, its FB pin goes below the undervoltage threshold and the PWRGD pin deasserts. Higher overcurrents when either VRSENSE > 100mV (fast comparator threshold) for more than 1s will trigger the same condition. This fault state can only be cleared by a UVLO at either VCC pin or a hard reset at the ON1 pin, as at time point 15, when ON1 is pulled below its reset threshold. The LTC4221 then reverts back to its reset state as between time points 1 and 2.
4221f
11
LTC4221
OPERATIO
VCCn CLEARS VCCn(UVL) ON1 > VON(RESET) + VON(RESETHYST) ON2 > VON(OFF), + VON(OFFHYST), CHECK GATE < VGATE(OV), TIMER < 0.4V ON1 > VON(OFF) + VON(OFFHYST), CHECK GATE < VGATE(OV), TIMER < 0.4V 1 VCCn 2 VCCn(UVL) VTMR(H) TIMER 1.9A VTMR(L) 20A 20A 3 4 56 7 8 ELECTRONIC CIRCUIT BREAKER ARMED, CHECK FILTER < VFILTER(TH), FAULT > VFAULT(TH) + VFAULT(HYST) CHANNEL 1 SLOW COMPARATOR ARMED CHANNEL 2 SLOW COMPARATOR ARMED 9 10 11 12 13 14 15
FAULT VFILTER(TH) 105A 1.8A
FILTER VON(OFF) + VON(OFFHYST) VON(RESET) + VON(RESETHYST) VON(OFF) + VON(OFFHYST) ON2 VON(OFF)
ON1
GATE1 100A VGATE(OV)
GATE2
SENSE1
SENSE2 FB1 > VFB(UV) + VFB(HYST) VOUT1
VOUT2
PWRGD1
PWRGD2
4221 F01
UVLO RESET
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VON1(RESET) 9.5A 9.5A 100A VGATE(OV) 25mV 9mV VSENSE(FC) VSENSE(SC) 9mV FB1 < VFB(UV) FB2 > VFB(UV) + VFB(HYST) FB2 < VFB(UV) OFF INITIAL TIMING CHANNEL 1 CHANNEL 2 NORMAL START-UP START-UP FAULT RESET
Figure 1. LTC4221 Operation
4221f
LTC4221
APPLICATIO S I FOR ATIO
Undervoltage Lockout An internal undervoltage lockout (UVLO) occurs if either VCC supply is too low for normal operation. The LTC4221 is kept in lockout mode in which the internal charge pumps are off, the GATE pins, TIMER are held low by internal N-channel MOSFET pull-downs and the FAULT latch reset, cutting off both channels. VCC1 has a low-to-high UVLO threshold of 2.5V with 110mV hysteresis. VCC2 has a lowto-high UVLO threshold of 0.8V with 25mV hysteresis. Both UVLOs have glitch filters that filter out dips that are less than 30s, allowing for bus supply transients. An additional requirement for normal operation is VCC1 VCC2. ON Pin Functions The ON1 pin serves as a global reset for the LTC4221. It has an internal reset comparator with a high-to-low threshold of 0.4V, a 25mV hysteresis and a high-to-low glitch filter of 15s. Pulling ON1 below this threshold will put the LTC4221 into a reset state in which the TIMER is pulled low by an internal N-channel MOSFET pull-down, the GATE pins are pulled low by separate internal 100A pull-downs and the FAULT latch resets. A low-to-high transition on the ON1 pin past the reset threshold releases the reset on the FAULT latch and both channels go into an off state.
BACKPLANE PCB EDGE CONNECTOR CONNECTOR (MALE) (FEMALE) VCC1 VCC2 LONG LONG Z1 RX1 10 CX1 100nF 1 16 R1 10k LONG Z1 = SMAJ10 * ADDITIONAL DETAILS OMITTED FOR CLARITY 10 ON1 VCC1
RSENSE1 Q1 0.004 IRF7413
R2 SHORT 10k
ON2 SENSE1 LTC4221* GATE1 GND 9 FB1 RF2 15k CTIMER 1F TIMER RF1 56k
(2a) Circuit
Figure 2. Simultaneous Power On/Off
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In addition to its global reset function, ON1 also serves as an on/off switch for channel 1. ON2 performs the same role for channel 2. Both pins have an off comparator with a high-to-low threshold of 0.821V and 30mV hysteresis. With these, ON1 and ON2 can be used to force a simultaneous or sequential power-up/power-down of the two channels. A simultaneous power-up and power-down is shown in Figure 2b. Both VCC pins clear their respective UVLO at time point 1 and both channels enter reset state. When ON1 clears its reset threshold, either ON1 or ON2 clears its off threshold, both GATEs < 0.4V and TIMER < 0.4V (time point 2), an initial timing cycle starts. At time point 4, the initial timing cycle completes and the LTC4221 checks that FILTER is low and FAULT is high. If both conditions are met, it then monitors the voltage of ON1 and ON2. As long as its ON pin has cleared its off threshold, each channel powers up regardless of the state of the other channel. Similarly, if its ON pin goes below its off threshold, each channel pulls its GATE pin down with an internal 100A pull-down and turns off its external MOSFET regardless of the state of the other channel. As the circuit in Figure 2a has its two ON pins shorted together, a simultaneous power-up is programmed at time points 4 to 5 and a simultaneous power down is programmed between time points 7 and 8. The timing waveforms in Figure 3 show a
1 2 34 56 78 VCCn VCCn(UVL) ONn VOUT1 3.3V 5A VOUT2 2.5V 5A 0.851V 0.821V 1.234V 1.9A 20A TIMER
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+
CLOAD1
GATEn
9.5A VTH
100A
VOUTn UVLO
4221 F02a
DISCHARGE BY LOAD
4221 F02b
INITIAL CHANNEL NORMAL TIMING START-UP
RESET
RESET STATE
(2b) Timing Waveforms
13
LTC4221
APPLICATIO S I FOR ATIO
12 VCCn VCCn(UVL) 34
ON1
0.851V
TIMER
1.234V 1.9A
GATE1
VOUT1
PWRGD1
ON2
GATE2
VOUT2 UVLO RESET INITIAL TIMING CHANNEL 1 START-UP CHANNEL 2 START-UP NORMAL
Figure 3. Sequential Power On/Off Timing Waveforms
sequential power up from time points 4 to 8 and a sequential power-down programmed from time points 9 to 11. To achieve this the circuit requires the functionality of the PWRGD1 pin and will be featured in the next section. The circuit in Figure 2a sits on a daughter board with staggered pins on its edge connectors. Supply voltage and ground connections are wired to long-edge connector pins while both ON pins are connected to a short-edge connector pin through a resistive divider. Until the connectors are fully mated, ON1 is pulled low and holds both channels in the reset state. When the connectors have properly seated, the ON pins are pulled above 0.851V and an initial timing cycle starts. This cycle is restarted by any transitions on the ON pins across their off thresholds and adds a further delay for the plug-in transients to die off before allowing a start-up cycle. The Typical Application circuit on the first page of this data sheet shows similar
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5 67 8 9 10 11 0.821V 0.4V 20A 20A 9.5A VTH VFB1 = 0.620V VFB1 = 0.617V DISCHARGE BY LOAD 100A 0.851V 0.821V 9.5A VTH DISCHARGE BY LOAD
4221 F03
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100A
OFF CHANNEL 1 OFF CHANNEL 2 NORMAL
considerations in the design of its PCB edge connectors, and the resistive dividers connected to ON1 and ON2 act as an external UVLO to override the internal one. An RC filter can be added at the ON1 pin to increase the delay time at card insertion to allow bus supply transients to stabilize. FB and PWRGD Pin Functions Each FB pin is used to detect undervoltage and overvoltage in its channel output voltage (VOUT) through a resistive divider. Each FB pin has an undervoltage comparator with a high-to-low threshold of 0.617V and 3mV hysteresis. The output of this comparator controls the channel's open-drain PWRGD output. During UVLO, both PWRGD pins are pulled low by internal N-channel MOSFET pulldowns. As both channels come out of UVLO, control of PWRGD1 is passed to FB1and control of PWRGD2 to FB2. Each PWRGD pin can be connected to a pull-up resistor to
4221f
LTC4221
APPLICATIO S I FOR ATIO
generate a logic high output to indicate that VOUT is valid. An internal high-to-low glitch filter helps to prevent negative voltage transients on each FB pin from deasserting its PWRGD. The relationship between glitch filter time and an FB pin transient voltage is shown in Figure 4. Using the functionality of the PWRGD1 pin, the LTC4221 can be configured to do sequential power-up and power-down as shown by the circuit in Figure 5. Referring back to Figure 3, ON2 is held low until VOUT1 ramps high enough for FB1 to exceed its undervoltage threshold at time point 5 when PWRGD1 ramps up, pulling ON2 high. At time point 7, the control logic sees ON2 exceeding its off threshold and so commences a start-up cycle for channel 2. Similarly, when ON1 is forced low by Q2 at time point 9, GATE1 is pulled low by its 100A pull-down while ON2 is held high by the
80 70 TA = 25C
GLITCH FILTER TIME (s)
60 50 40 30 20 10 0 0 20 40 60 80 100 120 140 160 180 200 FEEDBACK TRANSIENT (mV)
4221 F04
Figure 4. FB Comparator Glitch Filter Time vs Feedback Transient Voltage
BACKPLANE PCB EDGE CONNECTOR CONNECTOR (MALE) (FEMALE) VCC1 VCC2 LONG LONG SHORT R3 10k R6 10k ON/OFF SHORT R5 10 Q2 R1 10k R2 2k R4 10k
LONG Q2: 2N7002LT1 Z1: SMAJ10 * ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 5. Using PWRGD1 to Configure Sequential Power-Up/Power-Down
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R4 pull-up on PWRGD1. Its is only when channel 1 is powered off and VOUT1 discharges below its undervoltage threshold at time point 10 that PWRGD1's internal N-channel MOSFET pull-down is triggered and ON2 goes low. At time point 11, ON2 trips its off threshold and GATE2 pulls low with a 100A pull-down, powering off channel 2. For VOUT overvoltage detection, each FB pin has an overvoltage comparator with a low-to-high threshold of 0.822V and a low-to-high glitch filter of 18s. This threshold is designed to be 33% higher than the undervoltage threshold. If either FB pin trips this threshold, the fault latch is set, all GATE pins are pulled low with internal NFET pull-downs and the LTC4221 goes into a fault state. In the third function, each FB pin is used to control its channel's current limit during its start-up cycle. This will be featured in the Start-Up Cycle with Current Limit section. GATE Pin Functions Each GATE pin controls the gate of its channel's external N-channel MOSFET. Individual internal charge pumps powered by VCC1 guarantee a gate drive of minimum 4.5V and maximum 18V (internally clamped) for GATE1 and GATE2. During UVLO, the internal charge pumps are off and both GATE pins are pulled low by internal N-channel MOSFET pull-downs. Outside UVLO, when ON1 is below its off threshold, the charge pumps are on and GATE1 is held low by an internal 100A current pull-down. Once
RSENSE1 Q1 0.004 IRF7413 Z1 RX1 10 CX1 100nF VCC1 SENSE1 RF1 56k RF2 15k CTIMER 1F
4221 F05
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VOUT1 3.3V 5A VOUT2 2.5V 5A
1 16 6 10
ON1 ON2
+
CLOAD1
LTC4221* PWRGD1 GATE1 GND TIMER 9 FB1
15
LTC4221
APPLICATIO S I FOR ATIO
ON1 clears its off threshold and the initial timing cycle is complete, the GATE1 pin is pulled up by a 9.5A current source connected to the charge pump output during the channel start-up cycle. GATE1 can be servoed by adjusting the ramp up current to <9.5A to control the inrush current to the load during start-up. ON2 controls GATE2 in a similar manner but is overwritten by ON1's global reset function. During an overcurrent fault condition that sets the fault latch, both GATE pins are pulled down by their respective internal N-channel MOSFET pull-downs. During hot insertion of the PCB, an abrupt application of supply voltage charges the external MOSFET drain/gate capacitance. This can cause an unwanted gate voltage spike. An internal proprietary circuit holds both GATE pins low before the internal circuitry wakes up. This reduces the MOSFET current surges substantially at insertion. Electronic Circuit Breaker The LTC4221 features an electronic circuit breaker function that protects against supply overvoltage, externally generated fault conditions and shorts or excessive load current conditions on any of the supplies. If the circuit breaker trips, both GATE pins are immediately pulled to ground, the external N-channel MOSFETs are quickly turned OFF and FAULT is latched low. During the normal cycle, a supply overvoltage on channeln propagates via the VOUTn resistive dividers to the FBn pin. A supply overvoltage high enough to pull either FB pin above 0.822V for more than 18s will trip the circuit breaker. The circuit breaker can also be made to trip by externally forcing the bidirectional FAULT pin below 0.816V. The FAULT pin has 35mV of hysteresis. An internal glitch filter of 15s filters out noise on the FAULT pin. The slow comparator of channeln trips the circuit breaker if VRSENSEn = (VCCn - VSENSEn) is greater than its 25mV threshold for more than 15s. There may be applications where this inherent response time is not long enough, for example, because of excessive supply voltage noise. To adjust the response time of the slow comparator, a capacitor can be connected from the FILTER pin to GND. If this pin is left unused, each slow comparator's delay defaults to 15s. During normal operation, the FILTER output pin
ILOAD1
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is held low by an internal 1.8A pull-down current source. During an overcurrent condition on either channel as shown in Figure 6, the 1.8A pull-down on the FILTER pin becomes an internal 105A pull-up and CFILTER charges up. Once the FILTER pin voltage ramps past its low-tohigh threshold of 1.24V at time point 2, the electronic circuit breaker trips and the LTC4221 shuts down. The FILTER pin's internal 1.8A pull-down discharges CFILTER and holds FILTER low. Each slow comparator's response time from an overcurrent fault condition is:
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tFILTER =
1.24V * CFILTER + 15s 105A
(1)
Intermittent overloads may exceed the current limit as in Figure 7, but if the duration is sufficiently short, the FILTER pin may not reach the V FILTER(TH) threshold and the LTC4221 will not shut down. To handle this situation, the FILTER discharges with 1.8A whenever both VRSENSE are below 25mV. Any intermittent overload with an aggregate
1 1.24V VFILTER 1.8A NORMAL 2 CIRCUIT BREAKER TRIPS. GATE1, GATE2 AND FAULT PULL LOW 1.8A 105A 1.8A
4221 F06
SLOW COMPARATOR TRIP
Figure 6. A Continuous Fault Timing
A1 B1 A2 B2 A3 B3 ~25mV/RSENSE1
ILOAD2
~25mV/RSENSE2
105A 1.24V VFILTER 105A 105A 1.8A 1.8A
CIRCUIT BREAKER TRIPS 1.8A 1.8A
VGATE
4221 F07
SLOW COMPARATOR TRIP
SLOW COMPARATOR TRIP
SLOW COMPARATOR TRIP
Figure 7. Multiple Intermittent Overcurrent Condition
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LTC4221
APPLICATIO S I FOR ATIO
duty cycle of more than 1.8% will eventually trip the circuit breaker. Figure 8 shows the circuit breaker response time in seconds normalized to 1F. The asymmetric charging and discharging of FILTER is a fair gauge of MOSFET heating.
t CFILTER(F )
1 NORMALIZED RESPONSE TIME (s/F)
=
1.24V (105A * D) - 1.8A
1.24V t = CFILTER (F) 105 * D - 1.8
0.1
0.01 0 10 20 30 40 50 60 70 80 90 100 OVERLOAD DUTY CYCLE, D (%) 4221 F08
Figure 8. Circuit Breaker Filter Response for Intermittent Overload
1 VTMR(H) 1.9A TIMER FAULT VTMR(L)
FILTER 0.851V ONn 9.5A GATEn
SENSEn
VOUTn
4221 F09
RESET
INITIAL TIMING
Figure 9. Fast Comparator Trip Timing Waveforms
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(2) The fast comparators trip the circuit breaker to protect against fast load overcurrents if VRSENSE is greater than VSENSE(FC) (100mV) for 1s. The response time of each fast comparator is fixed at 1s nominal. The timing diagram in Figure 9 illustrates the operation of the LTC4221 when the load current conditions cause VRSENSE of channel 1 to exceed 100mV for more than 1s between time points 7 and 8. Figure 9 also illustrates when the LTC4221's electronic circuit breaker is armed. After the initial timing cycle, it is armed at time point 3. Arming the circuit breaker at time point 3 ensures that the system is protected against an overcurrent condition during the channel start-up cycle. At time point 4, the slow comparators are armed when the internal control loop is disengaged. Autoretry After a Fault Once the LTC4221 circuit breaker is tripped, FAULT is latched low and both GATE pins are pulled to ground. To clear the internal FAULT latch and to restart the LTC4221, its ON1 pin must be pulsed below its reset threshold (VON(RESET) = 0.4V) for at least 15s.
ELECTRONIC CIRCUIT BREAKER ARMED SLOW COMPARATORS ARMED 23 20A 45 20A 67 8 9 105A VFILTER(TH) 1.8A 0.4V VSENSE(FC) VSENSE(SC) CHANNEL START-UP NORMAL FAULT RESET
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LTC4221
APPLICATIO S I FOR ATIO
The LTC4221 can also be configured to automatically retry after a fault condition. As shown in Figure 10, the FAULT (which has an internal 3.8A pull-up current source) and both ON pins are connected together. The timing diagram in Figure 11 illustrates a simultaneous start-up sequence where the LTC4221 is powered up into a load overcurrent condition on channel 1. After the slow comparators are
BACKPLANE PCB EDGE CONNECTOR CONNECTOR (MALE) (FEMALE) VCC1 VCC2 LONG LONG Z1 R1 SHORT 1M CON1 0.47F LONG Q2: 2N7002LT1 Z1: SMAJ10 * ADDITIONAL DETAILS OMITTED FOR CLARITY RX1 10 CX1 100nF VCC1 SENSE1 GATE1 FB1 8 9 RF2 15k CTIMER 1F
4221 F10
FAULT
Figure 10. Using FAULT to Configure Autoretry
ELECTRONIC CIRCUIT BREAKER ARMED SLOW COMPARATORS ARMED 1 TIMER VTMR(H) 1.9A VTMR(L) 0.851V 0.4V VFILTER(TH) FILTER 9.5A GATE1 105A 23 20A 45 20A 67 8 9 2A
ONn, FAULT
SENSE1
VOUT1
4221 F11
RESET
INITIAL TIMING tINITIAL
Figure 11. Autoretry Timing Waveforms
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armed at the end of the start-up cycle at time point 4, slow comparator 1 immediately trips and FILTER ramps up. FILTER ramps past its high threshold at time point 6 and trips the circuit breaker. FAULT and both ON pins are pulled low by an internal N-channel MOSFET and overshoots below the 0.4V reset threshold of the ON1 pin. Once ON1 < 0.4V for more than 15s, the internal fault
RSENSE1 Q1 0.004 IRF7413 VOUT1 3.3V 5A VOUT2 2.5V 5A 1 16 7 10 ON1 ON2 FAULT GND
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+
CLOAD1 RF1 56k
LTC4221*
FILTER TIMER CFILTER 1nF
0.4V
0.851V
1.8A
VSENSE(FC) VSENSE(SC)
CHANNEL START-UP tSTARTUP
FILTER RAMP tFILTER
RESET tON
OFF
INITIAL TIMING tINITIAL
LTC4221
APPLICATIO S I FOR ATIO
C ON1 3.8A
latch is cleared and the FAULT pin sources a 3.8A pull-up current to charge up CON1. The typical delay tON is :
tON = (0.851V - 0.4V ) *
As shown in the timing diagram of Figure 11, the autoretry circuitry will attempt to restart the LTC4221 with a duty cycle:
Duty Cycle =
( tSTARTUP + tFILTER ) * 100%
tON + tINITIAL + tSTARTUP + tFILTER
tFILTER is defined in Equation 1 and tON is defined in Equation 3. tINITIAL, the initial timing cycle delay, is given in Equation 9 located in the Initial Timing Cycle section. tSTARTUP, the start-up cycle delay, is given in Equation 10 and found in the Start-Up Cycle Without Current Limit section. Using the capacitor values as shown in Figure 10, the Autoretry Duty cycle works out to be approximately 6%. Sense Resistor Consideration The fault current level at which the LTC4221's internal electronic circuit breaker trips is determined by sense resistors connected between each channel's VCC and SENSE pins. For both channels, the slow comparator trip current and the fast comparator trip current are given by equations (5) and (6) respectively. VSENSE(SC) 25mV ITRIP(SC) = = RSENSE RSENSE VSENSE(FC) 100mV ITRIP(FC) = = RSENSE RSENSE (5) (6)
The power rating of the sense resistor should be rated at the fault current level. Table 1 in the Appendix lists some common sense resistors. For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and each channel's VCC and SENSE pins are strongly recommended. The drawing in Figure 12 illustrates the connections between the LTC4221 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should
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CURRENT FLOW TO LOAD SENSE RESISTOR CURRENT FLOW TO LOAD
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(3)
TRACK WIDTH W: 0.03" PER AMP ON 1oz COPPER
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4221 F12
TO TO VCCn SENSEn
(4)
Figure 12. PCB Connections to the Sense Resistor
include good thermal management techniques for optimal sense resistor power dissipation. Calculating Current Limit For a selected RSENSE, the load current must not exceed ITRIP(SC). The minimum ITRIP(SC) is given by Equation 7:
ITRIP(SCMIN) =
where
VSENSE(SCMIN) 20.5mV = RSENSE(MAX) RSENSE(MAX)
(7)
R RSENSE(MAX) = RSENSE * 1 + TOL 100 The maximum ITRIP(SC) is given by Equation 8:
ITRIP(SCMAX) =
where
VSENSE(SCMAX) 29.5mV = RSENSE(MIN) RSENSE(MIN)
(8)
R RSENSE(MIN) = RSENSE * 1 - TOL 100 If a 7m sense resistor with 1% tolerance is used for current limiting, the nominal slow comparator trip current is 3.57A. From Equations 7 and 8, ITRIP(SCMIN) = 2.9A and ITRIP(SCMAX) = 4.26A. For proper operation, the minimum ITRIP(SC) must exceed the circuit maximum operating load current. For reliability purposes, the operation at the maximum trip current must be evaluated carefully. If necessary, two resistors with the same RTOL can be connected in parallel to yield a nominal RSENSE value that fits the circuit requirements.
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LTC4221
APPLICATIO S I FOR ATIO
Timer Function The TIMER pin controls the initial cycle and the channel start-up cycles with an external capacitor, CTIMER. There are two comparator thresholds: VTMR(H) (1.234V) and VTMR(L) (0.4V). In addition, the pin has a 1.9A pull-up current, a 20A pull-up current and a N-channel MOSFET pull-down. Initial Timing Cycle When the card is being inserted into the bus connector, the long pins mate first which brings up the supplies at time point 1 of Figure 13. The LTC4221 is in reset mode as the ON1 pin is low. Both GATE pins and the TIMER pin are pulled low. At time point 2, the short pin makes contact and both ON pins are pulled high. At this instant, a start-up check requires that both supply voltages be above UVLO, at least one ON pin be above 0.851V, both GATE pins < 0.4V and TIMER < 0.4V. When these four conditions are fulfilled, the initial cycle begins and the TIMER pin is pulled high with 1.9A. At time point 3, the TIMER reaches VTMR(H) and is pulled down below VTMR(L) by the Nchannel MOSFET pull-down, ending the initial cycle at time point 4. The initial cycle delay is:
tINITIAL = 1.234V *
CTIMER 1.9A
12 VCCn 0.851V
345
6
7
ONn
0.4V 1.234V 1.9A 20A 0.4V 9.5A VTH VOUT1 DISCHARGE BY LOAD
4221 F13
TIMER
GATE1
RESET STATE
INITIAL TIMING
CHANNEL 1 START-UP
NORMAL
Figure 13. Channel 1 Start-Up Without Current Limit
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At time point 4, the LTC4221 checks whether the FILTER pin is <1.24V and FAULT is > 0.851V. If both conditions are met, a channel start-up cycle commences. Start-Up Cycle Without Current Limit During a channel start-up cycle, the TIMER pin ramps up with a 20A internal pull-up so the start-up cycle delay is:
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tSTARTUP = (1.234V - 0.4V ) *
CTIMER 20A
(10)
At the beginning of the start-up timing cycle (time point 4), the LTC4221's electronic circuit breaker is armed and each channel has an internal 9.5A current source working with an internal charge pump to provide the gate drive to its external pass transistor. At time point 5, GATE1 reaches the external pass transistor threshold and VOUT1 starts to follow the GATE1 ramp-up. If the inrush current is below current limit, GATE1 ramps at a constant rate of:
VGATE IGATE = T CGATE
(11)
(9)
where CGATE is the total capacitance at the GATE1 pin. The inrush current through RSENSE1 can be divided into two components; ICLOAD due to the total load capacitance CLOAD and ILOAD due to the noncapacitive load elements. The load bypass capacitance typically dominates CLOAD. For a successful channel start-up without current limit, IINRUSH < active current limit. Due to the voltage follower configuration, the VOUT1 ramp rate approximately tracks VGATE1. The inrush current during a start-up cycle without current limit is :
V IINRUSH = CLOAD * OUT + ILOAD T V IINRUSH = CLOAD * GATE + ILOAD T I IINRUSH = CLOAD * GATE + ILOAD CGATE
At time point 6, VOUT1 is approximately VCC1 but GATE1 ramp-up continues until it reaches a maximum voltage. This maximum voltage is determined either by the charge pump or the internal clamp.
4221f
(12)
LTC4221
APPLICATIO S I FOR ATIO
Start-Up Cycle With Current Limit During a channel start-up cycle, if the inrush current as according to Equation (12) is large enough to cause a voltage drop greater than the active current limit threshold (VSENSE(ACL)) across the sense resistor, an internal servo loop controls the operation of the 9.5A current source at the GATE pin to regulate the load current to: IINRUSH = VSENSE(ACL) RSENSE (13)
The active current limit threshold for channel n has a component controlled by the voltage at the FBn pin. When FBn = 0V, VSENSE(ACL) = 9mV. As VOUTn and FBn ramp up, VSENSE(ACL) increases linearly until FBn reaches 0.5V, where VSENSE(ACL) saturates at 25mV. In this fashion, the inrush current is controlled by this "foldback" limiting that tends to keep the power dissipation in the external MOSFET constant during the start-up cycle. The timing diagram in Figure 14 illustrates the operation of the LTC4221 in a channel start-up cycle with limited inrush
12 3 4 56 78 9 A
VCCn
VONn
0.851V 0.4V 1.234V 1.234V 20A 0.4V
VTIMER
1.9A
VGATE2
9.5A
<9.5A VTH
9.5A
VOUT2
IRSENSE2
REGULATED AT VSENSE(ACL)(t)/RSENSE
REGULATED AT 25mV/RSENSE
RESET STATE
INITIAL TIMING
CHANNEL 2 START-UP
NORMAL CYCLE
Figure 14. Channel 2 Start-Up with Current Limit
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current as described by Equation 13. Between time points 5 and 6, the GATE2 pin ramps up with IGATE = 9.5A. At time point 6, the inrush current increases enough to trip VSENSE(ACL)(t) and an internal servo loop engages, limiting the inrush current to the level as in Equation 13 by decreasing IGATE (<9.5A). As a result, the ramp rate of both VGATE2 and VOUT2 decreases and VSENSE2 increases linearly until it saturates at 25mV at time point 7. At time point 8, the external MOSFET enters triode operation. IINRUSH drops as the ramp rate of VOUT2 falls below that of VGATE2 so IGATE reverts back to 9.5A. At time point 9, the internal servo loop to control IINRUSH is disengaged and channel 2 slow comparator is armed, ending the channel 2 start-up cycle. So if CLOAD2 is not fully charged up at this point, IINRUSH will be subject to the slow comparator threshold and actions as outlined in the Electronic Circuit Breaker section. For a successful channel start-up, the current limited part of the VOUT ramp-up (time points 6 and 8 of Figure 14) must not exceed the sum of start-up cycle delay as given by Equation 10 and the slow comparator response time as given by Equation 1. An example of an unsuccessful start-up is Figure 11 which shows a channel powering up into an overcurrrent at the load. The fast comparators of both channels are armed at the end of the initial timing cycle at time point 4 of Figure 14. If a short circuit during the start-up cycle overrides the servo loop and causes VRSENSE of either channel to exceed 100mV for more than 1s, the electronic circuit breaker trips and the LTC4221 enters the fault state. Frequency Compensation at Start-Up Cycle If a channel's external gate input capacitance (CISS) is greater than 600pF, no external gate capacitor is required at GATE to stabilize the internal current-limiting loop during start-up with current limit. The servo loop that controls the external MOSFET during current limiting has a unitygain frequency of about 105kHz and phase margin of 80 for external MOSFET gate input capacitances to 2.5nF. Power MOSFET
4221 F14
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DISCHARGE BY LOAD
Power MOSFETs can be classified by RDS(ON) at VGS gate drive ratings of 10V, 4.5V, 2.5V and 1.8V. Those rated for RDS(ON) at 10V VGS usually have a higher VGS absolute maximum rating than those at 4.5V and 2.5V. At low
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21
LTC4221
APPLICATIO S I FOR ATIO
supply voltages, the LTC4221 can drive any MOSFET rated with 4.5V or 2.5V gate drive. For higher supply voltages up to 13.5V, the LTC4221 can drive any MOSFET rated with a 10V or 4.5V gate drive. The selected MOSFET should fulfill two VGS criteria: 1. Positive VGS absolute maximum rating > LTC4221's maximum VGATE. 2. Negative VGS absolute maximum rating > supply voltage. The gate of the MOSFET can discharge faster than VOUT when shutting down the MOSFET with a large CLOAD. If one of the conditions cannot be met, an external zener clamp shown on Figure 15 can be used. The clamp network is connected from each channel's GATE to the VOUT pins. VGS is clamped in both directions and RG limits the current flow into the GATEn pin's internal zener clamp during transient events. A MOSFET with a VGS absolute maximum rating of 20V meets the two criteria for all the LTC4221 application ranges from 1V to 13.5V. Typically most 10V gate rated MOSFETs have VGS absolute maximum ratings of 20V or greater, so no external VGS zener clamp is needed. There are 4.5V gate rated MOSFETs with VGS absolute maximum ratings of 20V. In addition to the MOSFET gate drive rating and VGS absolute maximum rating, other criteria such as VBDSS, ID(MAX), RDS(ON) , PD, JA, TJ(MAX) and maximum safe operating area (SOA) should also be carefully reviewed. VBDSS should exceed the maximum supply voltage inclusive of spikes and ringing. ID(MAX) must exceed the maximum short-circuit current in the channel during a fault
RSENSE Q1 VCC D1* D2*
4221 F15
VOUT
RG 200 GATE *USER SELECTED VOLTAGE CLAMP (A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED) 1N4688 (5V) 1N4692 (7V): LOGIC-LEVEL MOSFET 1N4695 (9V) 1N4702 (15V): STANDARD-LEVEL MOSFET
Figure 15. Gate Protection Zener Clamp
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condition. RDS(ON) determines the MOSFET VDS which together with VRSENSE yields an error in the VOUT voltage. For example, at 1V VCC2, VDS + VRSENSE2 = 50mV gives a 5% VOUT2 error. At higher VCC voltages the VDS requirement can be relaxed in which case the MOSFET's thermal requirements (PD, TJ(MAX), SOA) may limit the value of RDS(ON). The power dissipated in the MOSFET is (ILOAD)2 * RDS(ON) and this should be less than the maximum power dissipation, PD, allowed in that package. Given power dissipation, the MOSFET junction temperature, TJ can be computed from the operating temperature (TA) and the MOSFET package thermal resistance (JA). The operating TJ should be less than the TJ(MAX) specification. The VDS * ILOAD figure must also be well within the manufacturer's recommended safe operating area (SOA) with sufficient margin. These three thermal parameters must not be exceeded for all conditions in a channel including normal mode operation, start-up with or without current limit, fault and autoretry after a fault. To ensure a reliable design, fault tests should be evaluated in the laboratory. VCC Transient Protection Good engineering practice calls for bypassing the supply rail of any analog circuit. Bypass capacitors are often placed at the supply connection of every active device, in addition to one or more large value bulk bypass capacitors per supply rail. If power is connected abruptly, the large bypass capacitors slow the rate of rise of the supply voltage and heavily damp any parasitic resonance of lead or PC track inductance working against the supply bypass capacitors. The opposite is true for LTC4221 Hot Swap circuits mounted on plug-in cards since controlling the surge current to bypass capacitors at plug-in is the primary motivation for the Hot Swap controller. In most cases, there is no supply bypass capacitor present on the powered supply voltage side of the MOSFET switch. Although wire harness, backplane and PCB trace inductances are usually small, these can create large spikes when large currents are suddenly drawn, cut off or limited. Abrupt intervention can prevent subsequent damage caused by a catastrophic fault but it does cause a large supply transient. These ringing transients appear as a fast edge on
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LTC4221
APPLICATIO S I FOR ATIO
the input supply line, exhibiting a peak overshoot to 2.5 times the steady-state value. This peak is followed by a damped sinusoidal response whose duration and period are dependent on the resonant circuit parameters. This can cause detrimental damage to board components unless measures are taken. The energy stored in the lead/trace inductance is easily controlled with snubbers and/or transient voltage suppressors. Even when ferrite beads are used for electromagnetic interference (EMI) control, the low saturating current of ferrite will not pose a major problem if the transient voltage suppressors with adequate ratings are used. The transient associated with a GATE turn off can be controlled with a snubber and/or transient voltage suppressor. Snubbers such as RC networks are effective especially at low voltage supplies. The choice of RC is usually determined experimentally. The value of the snubber capacitor is usually chosen between 10 to 100 times the MOSFET COSS. The value of the snubber resistor is typically between 3 to 100. When the supply exceeds 7V or EMI beads exist in the wire harness, a transient voltage suppressor and snubber are recommended to clip off large spikes and reduce the ringing. For supply voltages of 6V or below, a snubber network should be sufficient to protect against transient voltages. These protection networks should be mounted very close to each of LTC4221's two supply voltages using short lead lengths to minimize lead inductance. This is shown schematically in the Typical Application on the front page of this data sheet. In many cases, a simple short-circuit test can be performed to determine the need of the transient voltage suppressor. Additional overvoltage protection is provided by the FBn pins.
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PCB Layout Considerations A recommended layout for the SENSE resistors, the power MOSFETs, VCC transient protection devices and GATE drive components around the LTC4221 is shown in Figure 16. For proper operation of the LTC4221's electronic circuit breaker, a 4-wire Kelvin connection to each SENSE resistor is used. Also, PCB layout for the external N-channel MOSFETs emphasizes optimal thermal management of MOSFET power dissipation to keep JA as low as possible. The VCC transient protection devices are positioned close to the supply pins to reduce lead inductance and thus overshoot voltage. In Hot Swap applications where load currents can reach 10A or more, PCB track width must be appropriately sized to keep track resistance and temperature rise to a minimum. Consult Appendix A of LTC Application Note 69 for details on sizing and calculating trace resistances as a function of copper thickness. In the majority of applications, it will be necessary to use plated-through vias to make circuit connections from component layers to power and ground layers internal to the PC board. For 1oz copper foil plating, a good starting point is 1A of DC current per via, making sure the via is properly dimensioned so that solder completely fills any void. For other plating thicknesses, check with your PCB fabrication facility.
4221f
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23
LTC4221
APPLICATIO S I FOR ATIO
TRACK WIDTH W CURRENT FLOW TO LOAD RSENSE2 D CHANNEL 2 INPUT D W D D
RX2 Z2 CX2
R4
R3
ON2 16 VCC2 15 SENSE2 14 GATE2 13 FB2 12 PWRGD1 PWRGD2 11 GND 10 TIMER 9
GND
SENSE1
FILTER
GATE1
FAULT
VCC1
ON1
FB1
* * VIAS * * *
Z1 CX1 R1
1
2
3
4
5
6
7
8
RX1
R2
CHANNEL 1 INPUT
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CURRENT FLOW TO LOAD NOTE: DRAWING IS NOT TO SCALE *ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 16. Recommended Layout for LTC4221 RSENSE, Power MOSFETs and Feedback Networks
APPE DIX
Table 1 lists some current sense resistors that can be used with the circuit breaker. Table 2 lists some power MOSFETs that are available. Table 3 lists the web sites of several
Table 1. Sense Resistor Selection Guide
CURRENT LIMIT VALUE 1A 2A 2.5A 3.3A 5A 10A PART NUMBER LR120601R050 LR120601R025 LR120601R020 WSL2512R015F LR251201R010F WSR2R005F DESCRIPTION 0.05 0.5W 1% Resistor 0.025 0.5W 1% Resistor 0.02 0.5W 1% Resistor 0.015 1W 1% Resistor 0.01 1.5W 1% Resistor 0.005 2W 1% Resistor MANUFACTURER IRC-TT IRC-TT IRC-TT Vishay-Dale IRC-TT Vishay-Dale
4221f
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POWER MOSFET SO-8 G S S S W CHANNEL 2 OUTPUT CURRENT FLOW TO LOAD RF3 CTIMER RF4 LTC4221* VIAS
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* * * * *
GND TO LOAD
BOTTOM LAYER AND GND TRACE CFILTER RF2
RF1
D D D D RSENSE1 POWER MOSFET SO-8
G S S S
4221 F16
CHANNEL 1 OUTPUT
CURRENT FLOW TO LOAD
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manufacturers. Since this information is subject to change, please verify the part numbers with the manufacturer.
LTC4221
APPE DIX
Table 2. N-Channel Selection Guide
CURRENT LEVEL (A) 0 to 2 2 to 5 5 to 10 10 to 20 PART NUMBER MMDF3N02HD MMSF5N02HD MTB50N06V MTB75N05HD DESCRIPTION Dual N-Channel SO-8 RDS(ON) = 0.1, CISS = 455pF Single N-Channel SO-8 RDS(ON) = 0.025, CISS = 1130pF Single N-Channel DD Pak RDS(ON) = 0.028, CISS = 1570pF Single N-Channel DD Pak RDS(ON) = 0.0095, CISS = 2600pF MANUFACTURER ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor
Table 3. Manufacturers' Web Sites
MANUFACTURER TEMIC Semiconductor International Rectifier ON Semiconductor Harris Semiconductor IRC-TT Vishay-Dale Vishay-Siliconix Diodes, Inc. WEB SITE www.temic.com www.irf.com www.onsemi.com www.semi.harris.com www.irctt.com www.vishay.com www.vishay.com www.diodes.com
TYPICAL APPLICATIO S
Simultaneous Turn-On with Autoretry Function--Individual Current Limits
BACKPLANE CONNECTOR (FEMALE) VCC1 5V VCC2 3.3V PCB EDGE CONNECTOR (MALE) LONG RX1 10 RSENSE1 0.004
LONG Z1
R2 21k R1 3.16k
GND
LONG Z1, Z2: SMAJ10
CTIMER 470nF
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Q1 IRF7413 RSENSE2 0.007 Q2 IRF7413
CX1 100nF
Z2
R3 15k CX2 100nF
RX2 10
VOUT1 5V 5A VOUT2 3.3V 2.5A
RF3 20k RPG2 10k RPG1 10k
2 1 VCC1 ON1
3
4
15
14
13 FB2 12
SENSE1 GATE1 VCC2
SENSE2 GATE2
RF4 5.11k
16 7 10 9 8
CFILTER 1nF
ON2 LTC4221 FAULT GND TIMER FILTER
PWRGD2 PWRGD1
11 6
RF1 32.4k
PWRGD2 PWRGD1
FB1
5
RF2 5.11k
4221 TA02
4221f
25
LTC4221
TYPICAL APPLICATIO S
Simultaneous Turn-On with Autoretry Function--Linked Current Limits
BACKPLANE CONNECTOR (FEMALE) VCC1 3.3V VCC2 2.5V PCB EDGE CONNECTOR (MALE) LONG RX1 10
LONG Z1
R2 16.5k R1 4.22k
GND
LONG Z1, Z2: SMAJ10
CTIMER 470nF
BACKPLANE CONNECTOR (FEMALE) VCC1 3.3V VCC2 2.5V
PCB EDGE CONNECTOR (MALE) LONG RX1 10
LONG Z1
R2 21k R1 10k
GND
LONG Z1, Z2: SMAJ10
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RSENSE1 0.004
Q1 IRF7413 RSENSE2 0.004 Q2 IRF7413 RF3 14.3k
CX1 100nF
Z2
R3 12.4k CX2 100nF
RX2 10
VOUT1 3.3V 5A VOUT2 2.5V 5A
2 1 VCC1 ON1
3
4
15
14
13 FB2
SENSE1 GATE1 VCC2
SENSE2 GATE2
12
RF4 5.11k RPG2 10k RPG1 10k
16 7 10 9 8
CFILTER 1nF
ON2 LTC4221 FAULT GND TIMER FILTER
PWRGD2 PWRGD1
11 6
RF1 20k
PWRGD2 PWRGD1
FB1
5
RF2 5.11k
4221 TA03
Sequenced Turn-On
RSENSE1 0.004
Q1 IRF7413 RSENSE2 0.004 Q2 IRF7413
CX1 100nF
Z2
CX2 100nF
RX2 10
VOUT1 3.3V 5A VOUT2 2.5V 5A
RF3 14.3k
2 1 VCC1 ON1
3
4
15
14
13 FB2
SENSE1 GATE1 VCC2
SENSE2 GATE2
12
RF4 5.11k RPG2 10k
R3 14.3k
16
R4 10k
ON2 LTC4221 FAULT GND TIMER FILTER
PWRGD2 PWRGD1
11 6
RF1 20k
PWRGD2
7 10 9 8
FB1
5
RF2 5.11k
4221 TA04
CTIMER 470nF
CFILTER 1nF
4221f
LTC4221
TYPICAL APPLICATIO S
Sequenced Up/Down, Channel 1 Up First, Down Last
BACKPLANE CONNECTOR (FEMALE) VCC1 3.3V VCC2 2.5V ON 0V TO 3.3V OR 3.3V TO 0V PCB EDGE CONNECTOR (MALE) LONG RX1 10 RSENSE1 0.004 Q1 IRF7413 RSENSE2 0.004 Q2 IRF7413
LONG Z1 SHORT
R3 8.06k R2 6.98k R1 17.8k
FAULT GND
SHORT LONG
D1: 1N4148 Z1, Z2: SMAJ10
CTIMER 470nF CFILTER 1nF
PACKAGE DESCRIPTIO
.015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE
0 - 8 TYP
.229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Z2
CX1 100nF R5 13k
RX2 10 CX2 100nF
VOUT1 3.3V 5A VOUT2 2.5V 5A
RF3 14.3k
R4 10k
2 D1 1 VCC1 ON1
3
4
15
14
13 FB2 12
RF4 5.11k
SENSE1 GATE1 VCC2
SENSE2 GATE2
16 7 10 9 8
ON2 LTC4221 FAULT GND TIMER FILTER
PWRGD2 PWRGD1
11 6
RF1 20k
FB1
5
RF2 5.11k
4221 TA05
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005
.254 MIN
.150 - .165
.0165 .0015
.0250 BSC
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
RECOMMENDED SOLDER PAD LAYOUT .0532 - .0688 (1.35 - 1.75) .004 - .0098 (0.102 - 0.249)
.009 (0.229) REF
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
GN16 (SSOP) 0204
1
23
4
56
7
8
4221f
27
LTC4221
TYPICAL APPLICATIO
BACKPLANE CONNECTOR (FEMALE) VCC1 3.3V VCC2 2.5V ON 0V TO 3.3V OR 3.3V TO 0V
PCB EDGE CONNECTOR (MALE) LONG RX1 10
LONG Z1 SHORT
R3 12.1k R2 20.5k R1 23.7k
FAULT GND
SHORT LONG
D1: 1N4148 Z1, Z2: SMAJ10
CTIMER 470nF R5 9.53k CFILTER 1nF
RELATED PARTS
PART NUMBER LTC1421 LTC1422 LTC1642 LTC1645 LTC1647 LTC4210 LTC4211 LTC4230 LTC4251 LTC4252 LTC4253 DESCRIPTION 2-Channel, Hot Swap Controller Single Channel, Hot Swap Controller in SO-8 Fault Protected, Hot Swap Controller Dual Channel Hot Swap Controller Dual Channel, Hot Swap Controller Single Channel, Hot Swap Controller in SOT-23 Single Channel, Hot Swap Controller in MSOP Triple Channel, Hot Swap Controller -48V Hot Swap Controller in S0T-23 -48V Hot Swap Controller in MSOP -48V Hot Swap Controller and Sequencer COMMENTS 24-Pin, Operates from 3V to 12V and Supports -12V Operates from 2.7V to 12V, System Reset Output Operates up to 16.5V, Overvoltage Protection to 33V 3.3V, 5V and 12V Supplies Operates from 1.2V to 12V, Power Sequencing Operates from 2.7V to 16.5V Operates from 2.7V to 16.5V, Multifunction Current Control 2.5V to 16.5V, Multifunction Current Control 1.7V to 16.5V, Multifunction Current Control -48V Hot Swap Controller, Active Current Limiting Active Current Limiting With Drain Acceleration Active Current Limiting With Drain Acceleration and Three Sequenced Power Good Outputs
LTC1643AL/LTC1643AH PCI Hot Swap Controllers
28
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 FAX: (408) 434-0507 www.linear-tech.com
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Sequenced Up/Down, Channel 2 Up First, Down Last
RSENSE1 0.004 Q1 IRF7413 RSENSE2 0.004 Q2 IRF7413
Z2
CX1 100nF R6 10k R4 23.2k
RX2 10 CX2 100nF RF3 14.3k
VOUT1 3.3V 5A VOUT2 2.5V 5A
VCC1 ON1 D1 ON2
SENSE1 GATE1 VCC2
SENSE2 GATE2 FB2
RF4 5.11k
PWRGD2 LTC4221 PWRGD1
RF1 20k
FAULT GND TIMER FILTER
FB1
RF2 5.11k
4221 TA06
4221f LT/TP 0604 1K * PRINTED IN THE USA
(c) LINEAR TECHNOLOGY CORPORATION 2004

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